Implementation of iscan cell for self-resetting dynamic circuit

ABSTRACT

A method and a circuit for testing an integrated circuit are disclosed. In one embodiment, a self-resetting dynamic circuit, also known as a fireball circuit, contains a scan circuit and at least one Set Dominant Latches (“SDL”) where each SDL includes a keeper node. When scan clock is active, the scan data propagates from the scan circuit to the self-resetting dynamic circuit through the keeper node.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the field of integratedcircuits and, more specifically, the present invention relates to amechanism for testing an integrated circuit.

2. Description of the Related Art

Integrated circuits are becoming more densely packed with increasingnumbers of individual circuit elements. It is common for a single chipto have thousands of individual elements that include millions oftransistors. With the increasing number of individual elements, testingeach element becomes more difficult to achieve. A conventional testmechanism used in the past for testing the integrated circuit is a scantest.

A scan test is typically performed by a scan circuit, also known as ascan cell. The scan circuit usually propagates scan data with testpatterns where the test patterns are, subsequently, applied to theinputs of the integrated circuit. Depending on the test pattern, theresponses or results of the integrated circuit to the test pattern canprovide an accurate indication of the existence or non-existence ofdefects.

However, with recently developed high-speed circuitry, the scantechnology used in the past may be inadequate since a conventional scancircuit is typically too slow for scanning the data through thehigh-speed circuitry.

SUMMARY OF THE INVENTION

A device for testing an integrated circuit includes a self-resettingdynamic circuit having a keeper node and a testing circuit that iscoupled to the keeper node. The testing circuit is configured to testthe self-resetting dynamic circuit in response to at least one testclock.

Additional features and benefits of the present invention will becomeapparent from the detailed description, figures and claims set forthbelow.

DESCRIPTION OF THE DRAWINGS

The present invention will be understood more fully from the detaileddescription given below and from the accompanying drawings of variousembodiments of the invention, which, however, should not be taken tolimit the invention to the specific embodiments, but are for explanationand understanding only.

FIG. 1 is a block diagram illustrating an embodiment of a scan circuit.

FIG. 2 is a circuit diagram illustrating an embodiment of a scan circuitfor testing a self resetting dynamic circuit.

FIG. 3 is a circuit diagram illustrating an embodiment of a scan circuithaving a keeper node.

FIG. 4 is a circuit diagram illustrating an embodiment for implementinga tri-state function.

FIG. 5 is a clock waveform illustrating an embodiment of scan clocks.

FIG. 6 is a block diagram illustrating an embodiment of scan process forscanning.

FIG. 7 is a flowchart illustrating one embodiment of scan process forscanning.

DETAILED DESCRIPTION

A method and a system for testing a self-resetting dynamic circuit, alsoknown as a fireball circuit, including a scan circuit and a SDL having akeeper node are described.

In the following description, for purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present invention. It will be apparent, however, toone skilled in the art that the present invention can be practicedwithout these specific details. In other instances, well-knownstructures and devices are shown in block diagram form in order to avoidobscuring the present invention.

It is understood that the present invention may be comprised oftransistor circuits that are readily manufacturable using well-knownCMOS (complementary metal-oxide semiconductor) technology, or otherequivalent semiconductor manufacturing processes. In addition, thepresent invention may be implemented with other manufacturing processesfor making digital devices.

While in the following discussion the present invention is presentedwith respect to implementation in a microprocessor, the presentinvention is not limited to that implementation. Implementations forgenerating clock signals for various digital devices such as discretelogic devices, memory devices, devices either on the same or separatechips, communications devices, etc., are within the scope of the presentinvention.

OVERVIEW

A mechanism for testing a self-resetting dynamic circuit (“SRDC”), alsoknown as a fireball circuit, using a scan circuit is disclosed. In oneembodiment, the SRDC, which is coupled to a scan circuit, contains atleast a Set Dominant Latch (“SDL”). The SDL is a dynamic state deviceused for holding a logic state. The SDL further includes a keeper node,which, in one embodiment, is able to receive the scan data. For example,when the scan clock is active, the scan data propagates from the scancircuit to the SRDC through the keeper node. The scan data as discussedpreviously may contain a set of specific test patterns where eachspecific test pattern indicates a specific circuit defect. In analternative embodiment, a tri-state device may be used to prevent datacontention between the data from the scan circuit and the data from theSRDC.

FIG. 1 is a block diagram 100 illustrating an embodiment of a scancircuit for testing a SRDC. Referring back to FIG. 1, a scan cell block102, a logic block 104, a SDL block 108, and two combinational logicblocks 106, 110 are disclosed. Other logic blocks could be added inblock diagram 100.

In one embodiment, scan cell 102 receives scan input data S_(IN) withtest patterns, a scan clock A (“SCa”) and a scan clock B (“SCb”). Whilethe output of scan cell 102 is fed to the input of logic 104, the outputof logic 104 is the scan output data S_(OUT). The scan data generated byscan cell 102, in one embodiment, is also fed to SDL 108.

In one embodiment, combinational logic block 106 receives the data inputD_(IN) and the clock Fclk which may also be a system clock.Combinational logic block 106 may perform various logical functions,such as, for example, multiplication and addition functions. The resultof the combinational logic block 106 is latched at SDL 108. The outputof SDL 108 is coupled to the input of combinational logic block 110. Theoutput of combinational logic block 110 is output at D_(OUT). In oneembodiment, Fclk is distributed to various functional blocks as well aslatches, such as, for example, combinational logic blocks 106, 110 andSDL 108.

Fclk is turned off and SCa and SCb are turned on when the scan mode ortesting mode is active. The scan data, which may contain test patterns,are scanned into SDL 108. Once SDL 108 receives the scan data, scanclocks SCa, SCb are turned off and Fclk is turned back on. After scanmode is switched to the system mode, the functional blocks, such as, forexample, combinational logic block 110, perform logic functions using.the data stored in SDL 108. Since SDL 108 contains the scan data, theresults of the functional blocks, such as combinational logic clock 110,can be predicted. When the functional blocks complete the implementationof the scan data, Fclk is again turned off and SCa, SCb are turned backon. When the results of the functional blocks are scanned out, theresults are further compared with the expected (or predicted) answerswith the outcome of the comparison indicating, at least in part, whetherthe functional blocks contain defects or not.

FIG. 2 is a circuit diagram 200 illustrating an embodiment of a scancircuit for testing a SRDC. Referring back to FIG. 2, block 202 andblock 204 are described. In one embodiment, block 202 is a scan circuitor scan cell while block 204 includes a SDL. In one embodiment, scancircuit is used to test the SRDC using scan data, such as, for example,test data with patterns. The SDL is a dynamic latch that is capable ofstoring a logic value. In one embodiment, a SDL can receive scan datafrom the scan circuit through its keeper node.

Block 202 contains two pass gates 210, 214, two inverters, 212, 216, anda tri-state device 218. The function of a pass gate 210 or 214 is toallow a signal to pass on a first condition and to prevent a signal topass on a second condition. For example, if SCa is active, pass gate 210allows S_(IN) to pass and if SCa is inactive, pass gate 210 preventsS_(IN) from passing through pass gate 210. In one embodiment, tri-statedevice 218 functions as an open circuit when SCa is in one condition andperforms an inverter function when SCa is in another condition. Forexample, if SCb is active, tri-state device 218 functions as an inverterand if SCb is inactive, tri-state device 218 functions as an opencircuit.

Pass gate 210 receives S_(IN) and SCa and the output of the pass gate210 is connected to the input of inventor 212. The input of pass gate214 is connected to the output of inverter 212 and the control input ofpass gate 214 is connected to SCb. The output of pass gate 214 isconnected to the input of inverter 216 and the output of the 216 is thescan output, S_(OUT), S_(OUT), is also fed back to the input oftri-state device 218. Tri-state device 218 receives SCb, which controlstri-state device 218. The output of the tri-state device 218 isconnected to the input of inverted 216.

In one embodiment, SDL 204 is a high-speed dynamic latch consisting oftwo PMOS transistors P1, P2, three NMOS transistors, N1, N2, N3, and atri-state device 220. The source terminal of P1 is connected to apositive voltage supply and the drain terminal of P1 is connected tonode A, which is the output of the circuit. The gate terminal of P1receives the data input, D_(IN). The source terminal of N2 is connectedto a ground voltage supply and the drain terminal of N2 is connected tothe source terminal of N1. The gate terminal of N2 receives Fclk. Thedrain terminal of N1 is connected to the node A and the gate terminal ofN1 is connected to D_(IN).

The source terminal of N3 is connected to the ground voltage supply andthe drain terminal of N3 is connected to the source terminal of N1. Thegate terminal of N3 is coupled to a keeper node. The source terminal ofP2 is connected to the positive voltage supply and the drain terminal ofP2 is coupled to the node A. The gate terminal of P2 is connected to thekeeper node. The input terminal of tri-state device 220 is connected tothe node A and the output of tri-state device 220 is connected to thekeeper node. Tri-state device 220 also receives SCa, which controlstri-state device 220. The output of pass gate 210 is also connected tothe keeper node.

In operation, when Fclk is active and D_(IN) is logic 0, node A is logic1because P1 is on and N1 is off. Since Fclk is active, SCa and SCb areinactive. Because SCa is off, tri-state device 220 functions as aninverter. Since node A is logic 1, the output of tri-state device 220 islogic 0, which drives the keeper node to logic 0. When the keeper nodehas a logic value 0, P2 is turned on and N3 is turned off. When P2 is onand N3 is off, the logic value 1 at D_(OUT) is retained.

When Fclk is off, and SCa and SCb are on, tri-state device 220 functionsas an open circuit and pass gate 210 is on. When pass gate 210 is on,S_(IN) passes through pass gate 210 to the keeper node and SDL 204 is,subsequently, re-programmed to store S_(IN). It should be appreciatedthat the keeper node is sensitive to the loading because the keeper nodeis the storage element for SDL 204. Consequently, the loading on thekeeper node, in one embodiment, should be small but yet it is largeenough to change the value of the keeper node.

FIG. 3 illustrates an embodiment of a circuit 300 having a SDL with akeeper node. Referring back to FIG. 3, a scan cell 302 and an SDL 304are disclosed. SDL 304 and block 204 of FIG. 2 are similar circuits. Inone embodiment, scan cell 302 is a flip-flop scan circuit, whichconsists of two inverters I1, I2, four PMOS transistors, P4, P5, P6, P7,four NMOS transistors, N4, N5, N6, N7, and a tri-state device T2.

Transistors P6 and N6, in one embodiment, form a pass gate 210 andtransistors P7 and N7 form a pass gate 214. Moreover, transistors P4 andN4 form an inverter 212 and transistors P5 and N5 form an inverter 216.Other logic devices may be added to circuit 300, but they are notnecessary to understanding the invention.

In operation, when scan clocks, SCa and SCb are active and Fclk isinactive, pass gate 210 functions as a passing circuit and T1 functionsas an open circuit. Once T1 is off and pass gate 210 is on, the logicstage at the keeper node may be programmed in response to S_(IN).Reprogram a SDL through a keeper node enhances the speed of reprogram.In other words, it takes less time to reprogram SDL using a keeper node.

When SCb is active, pass gate 214 is on which causes the output ofinverter 212 to be connected to the input of inverter 216. Because SCbis active, which causes T2 to function as an inverter, the feedback loopfrom the output of inverter 216 to the input of inverter 216 through T2is formed. Other types of scan cell may also be used in the presentinvention.

FIG. 4 is a circuit diagram 400 illustrating an embodiment forimplementing a tri-state function. Two PMOS transistors P10, P11 and twoNMOS transistors N10, N11, and an inverter 15 are shown in FIG. 4. Itshould be appreciated that other types of transistor may be used incircuit diagram 400 to perform the same functions.

The source terminal of P10 is coupled to a positive voltage supply andthe drain terminal of P10 is connected to the source terminal of P11.The gate terminal of P10 is connected to a control input terminal 404.The drain terminal of P11 is connected to an output terminal 408. Thegate terminal of P11 is connected to a data input terminal 406. Thedrain terminal of N10 is connected to the output terminal 404 and thesource terminal of N10 is connected to the drain terminal of N11. Thegate terminal of N10 is also connected to the data input terminal. Thesource terminal of N11 is connected to a ground voltage supply and thegate terminal of N11 is connected to the output of 15. The input of 15is connected to the control input terminal 404.

In operation, when the control input terminal 404 is logic 0, both P10and N11 are on, which causes circuit diagram 400 to function as aninverter. If the control input is logic 1, both P10 and N11 are off,which causes circuit diagram 400 to function as an open circuit. Othertypes of tri-state device may be used in this present invention toperform similar functions.

FIG. 5 is clock waveform 500 illustrating one embodiment of scan andsystem clocks. Waveforms of scan clocks, SCa, SCb, and waveforms ofsystem clock Fclk are shown in FIG. 5. As discussed previously,overlapping clock phase between the system clock and scan clocks is notpermitted. Accordingly, when Fclk is active, SCa and SCb are inactiveand similarly, when SCa and SCb are active, Fclk is inactive. In otherwords, when Fclk cycle is active, the scan clock cycles cannot beactive. In an alternative embodiment, scan clocks SCa and SCb arenon-overlapping scan clocks. For example, when SCa is 1, SCb cannot be 1at the same time.

FIG. 6 is a block diagram 600 illustrating an embodiment of scan processfor testing SRDC. Block 602 shows the suspension of the system clockFclk. When Fclk is off and scan clocks are on, the logic state stored atthe keeper node may be erased as shown in block 604. At block 606, thelogic state at SDL is reset in response to the scan data via the keepernode. Other blocks may be added, but they are not necessary tounderstanding the present invention.

FIG. 7 is a flowchart 700 illustrating one embodiment of scan processfor testing the SRDCs. The process starts at the start block andproceeds to block 702 where the process suspends a SRDC clock. Theprocess turns on scan clocks SCa and SCb at block 706. After SCa and SCbare active, the logic state stored at SDL is erased through the keepernode at block 707. After block 707, the process proceeds to block 708.At block 708, the process scans or flushes scan data having testpatterns into the keeper node in response to SCa and Scb. After block708, the process, at block 710, suspends scan clocks SCa, SCb andresumes the system clock Fclk. After block 710, the process proceeds toblock 712.

At block 712, the SRDC performs its logic functions in response to Fclkand the data stored at the keeper nodes. After block 712, the processsuspends Fclk at block 714 and subsequently, resumes scan clocks SCa,SCb. After block 714, the process moves to block 716. At block 716, theresult from the execution of the scan data is flushed out. The resultis, subsequently, compared with the expected data. The outcome of thecomparison is used to indicate whether the SRDC has any defects. Afterblock 71.6, the process moves to the end block where the process ends.

Whereas many alterations and modifications of the present invention willno doubt become apparent to a person of ordinary skill in the art afterhaving read the foregoing description, it is to be understood that thevarious embodiments shown and described by way of illustration are in noway intended to be considered limiting. Therefore, references to detailsof various embodiments are not intended to limit the scope of theclaims, which in themselves recites only those features regarded asessential to the invention.

Thus, a method and a system for testing SRDCs using a scan circuit havebeen described.

We claim:
 1. A device comprising: a self-resetting dynamic circuit(“SRDC”) having a data output; and a testing circuit coupled to the dataoutput and having a keeper node and a set-dominant latch to test theSRDC in response to at least one test clock.
 2. The device of claim 1,wherein the testing circuit applies testing data to the keeper node. 3.The device of claim 1 further comprising a tri-state circuit coupled tothe SRDC to prevent data contention.
 4. The device of claim 1, whereinthe testing circuit is a scan circuit including two scan clocks.
 5. Thedevice of claim 1, wherein the keeper node is located between acombination logic and a latch feedback.
 6. The device of claim 1,wherein the keeper node stores logic states.
 7. A method for testing acircuit comprising: suspending a self-resetting dynamic circuit (“SRDC”)clock; erasing logic state stored at a keeper node of a SRDC; andscanning testing data from a scan circuit to the SRDC through the keepernode.
 8. The method of claim 7, wherein erasing the logic state storedat a keeper node further includes utilizing a tri-state device tosuspend a feed back loop used to maintain a previous logic value.
 9. Themethod of claim 7, wherein the scanning testing data further comprising:flushing scan data into a scan chain in response to a first and secondscan clocks; suspending the first and second scan clocks; resuming theSRDC clock; executing the SRDC for a predefined number of cycles;suspending the SRDC clock and stopping execution; resuming the first andsecond scan clocks; and capturing a result of execution of the SRDC. 10.An apparatus for testing a circuit comprising: means for suspending aself-resetting dynamic circuit (“SRDC”) clock; means for erasing logicstate stored at a keeper node of a SRDC; and means for scanning testingdata from a scan circuit to the SRDC through the keeper node.
 11. Theapparatus of claim 10, wherein the means for erasing logic state furtherincludes means for utilizing a tri-state device to suspend a feed backloop used to retain previous logic value.
 12. The apparatus of claim 10,wherein the means for scanning testing data further comprising: meansfor flushing scan data into scan chain in response to a first and secondscan clocks; means for suspending the first and second scan clocks;means for resuming the SRDC clock; means for executing the SRDC for apredefined number of cycles; means for suspending the SRDC clock andstopping execution; means for resuming the first and second scan clock;and means for capturing a result of execution of the SRDC.
 13. A circuitfor testing a logic circuit comprising: a first transistor havingsource, drain and gate terminals, the source terminal of the firsttransistor being coupled to a first power supply voltage, the drainterminal of the first transistor being coupled to a first node, the gateterminal of the first transistor receiving a data input; a secondtransistor having source, drain and gate terminals, the source terminalof the second transistor being coupled to a second node, the drainterminal of the second transistor being coupled to the first node, thegate terminal of the second transistor receiving the data input; a thirdtransistor having source, drain and gate terminals, the source terminalof the third transistor being coupled to a second power supply voltage,the drain terminal of the third transistor being coupled to the secondnode, the gate terminal receiving a SRDC clock signal; a fourthtransistor having source, drain and gate terminals, the source terminalof the fourth transistor being coupled to the first power supplyvoltage, the drain terminal of the fourth transistor being coupled tothe first node, the gate terminal of the fourth transistor being coupledto a third node; a fifth transistor having source, drain and gateterminals, the source terminal of the fifth transistor being coupled tothe second power supply voltage, the drain terminal of the fifthtransistor being coupled to the second node, the gate terminal of thefifth transistor being coupled to the third node, a first tri-statedevice having an input, an output, a first clock input, and a secondclock input, the input of the first tri-state device being coupled tothe first node, the output of the first tri-state device being coupledto the third node, the first clock input of the first tri-state devicebeing coupled to a first scan clock, the second clock input of the firsttri-state device being coupled to a negative first scan clock; and afirst scan pass gate having an input, output, and clock input, the inputof the first scan pass gate being receiving a scan data, the output ofthe first scan pass gate being coupled to the third node, the clockinput of the first scan pass gate receiving the first scan clock. 14.The circuit of claim 13 further comprising: a first inverter having aninput and an output, the input of the first inverter being coupled tothe third node; a second scan pass gate having an input, an output, anda clock input, the input of the second scan pass gate being coupled tothe output of the first inverter, the clock input of the second scanpass gate receiving a second scan clock, a second inverter having aninput and an output, the input of the second inverter being coupled tothe output of the second scan pass gate; and a second tri-state devicehaving an input, an output, a first clock input, and a second clockinput, the input of the second tri-state device being coupled to theoutput of the second inverter, the output of the second tri-state devicebeing coupled to the input of the second inverter, the first clock inputof the second tri-state device being coupled to the second scan clock,the second clock input of the second tri-state device being coupled to anegative second scan clock.
 15. A circuit comprising: a self-resettingdynamic circuit (“SRDC”) having at least one set dominant latch (“SDL”);and a scan circuit coupled to the SDL to scan data through the SRDC inresponse to at least one scan clock, when executed, the circuit causesthe scan circuit to: suspend a system clock; erase logic state stored atthe SDL; and scan the scan data from the scan circuit to the SDL. 16.The circuit of claim 15, further comprising a tri-state device coupledto the SRDC and configured to prevent store contention.
 17. The circuitof claim 15, further comprising two non-overlapping scan clocks coupledto the scan circuit.
 18. The circuit of claim 15, wherein the SDLfurther including a keeper node, the keeper node configured to receivethe scan data.
 19. The device of claim 1 further comprising a scan inputcircuit coupled to provide data to the testing circuit via the keepernode in response to at least one scan clock.
 20. The device of claim 1further comprising a scan input circuit coupled to receive data from thetesting circuit via the keeper node in response to at least one scanclock.